Time delay device

ABSTRACT

This invention relates to time delay devices and more particularly to electronic time delay devices that have particular but not exclusive application as a time delay means for repeating circuit interrupters or reclosers.

I United States Patent [151 3,662,220 Riebs 1 May 9, 1972 54] TIME DELAYDEVICE 2,845,581 7/1958 Hodges et al. ..3l7/36 2,875,382 2/1959 Sandinet al. ..317/51 [72] Inventor. Richard E. Riebs, Hales Comers, WIS.2,895,084 7/l959 siedband 1 7/22 [73] Assignee: McGraw-Edison Company,Milwaukee, 5, l 960 Title t i --3 17/60 Wi 2,942,155 6/1960 Loeffler...1 7/22 2,961,582 11/1960 Ford ..3l7/22 I221 F1|ed= 1959 2,673,956 3/1954Beard ..324/68 [21] APPL 00 5 7 2,934,701 4/1960 Weisberg........3l7/14l 2,977,510 3/l96l Adamson ..3 17/36 U.S. TD, 3 17/22, 3 l R,Priniar Examiner-J, D, Tramme" /1 S Anorney-Charles A. Prudell [51]lnt.Cl. ..H0lh 47/18 [58] Field ofSearch ..317/148.S, 36, 51, 22, 33;[57] ABSTRACT This invention relates to time delay devices and moreparticu- [56] References Cited larly to electronic time delay devicesthat have particular but not exclusive application as a time delay meansfor repeating UNITED STATES PATENTS circuit interrupters or reclosers.

2,468,418 4/1949 Thumim ..3 17/36 28 Claims, 12 Drawing FiguresPATENTEDHAY 9 1912 sum 2 [1F 5 IN V EN TOR.

Richard E. Riebs PATENTEDMAY 9 I972 SHEET 3 UP 5 RL'c/mrd 15. R4665r/fttorney afttarng PATENTEDMY 9 1972 SHEET 5 [IF 5 TIME DELAY DEVICEMost protective devices utilized in electrical power and distributioncircuits have inverse time-current characteristics, that is, they willoperate rapidly upon the occurrence of a high fault current and willoperate relatively slower upon smaller fault currents.

It is common practice to utilize a variety of protective devices havingtime-current characteristics of difi'erent shapes and slopes in a singleelectrical system. For example, a distribution system may be providedwith a repeating circuit interrupter or recloser connected in serieswiththe main line and located adjacent the source of power and fusesdisposed in feeder lines radiating from the main 'line. Because themajority of faults in such systems are temporary in nature, and willclear in a relatively short time, it is common to arrange for theexecution of a series of rapid opening and reclosing operations by therepeating'circuit interrupter, so that the period in which the systemremains'energized is shorter than the time necessary for the fuseelements to melt. If the fault does not clear during this initial seriesof rapid operations, they are followed by a second series of operationsin which the interrupter contacts remain closed for a period ofsufficient length'to melt the fuse elements. This time delay, however,must not be of such duration that damage to the system itself willresult. An

optimum timing relationship for a wide range of fault current values canbest be achieved by utilizing a repeating circuit interrupter orrecloser having time-current characteristics which closely parallelthose of the other protective devices with which it is coordinated.

Prior art time delay devices generally utilized in reclosers andrepeating circuit interrupters are either hydraulic, mechanical orelectromagnetic. The hydraulic time delay devices, such as dash pots,are not entirely satisfactory because temperature changes tend to changethe viscosity of the hydraulic fluid and, as a result, the time-delaycharacteristic of the device. Electromagnetic time delay devices, suchas induction relays, are also unsatisfactory because the induction disccannot be rapidly reset after the disappearance of a fault, because'theinertia of the induction disc tends to result in coasting, and becausethe pull-in current of such devices is substantially greater than theirdropout current and as a result the device cannot reset after thedisappearance of a fault unless there was a sufi'icient current drop.Another shortcoming of prior art time delay devices are their largenumber of moving parts which greatly increases maintenance costs andinherently subjects them to changes in their time-currentcharacteristics due to wear. Also, because the speed of the mechanicalcomponents of these devices are, of course, dependent on the magnitudeof the fault current, they are extremely inaccurate at very low valuesof fault current. A further disability of prior art time delay devicesis that in any given device the time current characteristics arerelatively inflexible. As a result of the latter, prior art devicesdesigned for coordination with one type of secondary protective devicecannot conveniently be adapted for use with another.

It is an object of the invention to provide a new and improved timedelay device.

It is another object of the invention to provide an electronic timingdevice which is particularly, but not exclusively, adapted for use withrepeating circuit interrupters.

It is a further object of the invention to provide an electronic timedelay device wherein the slope and/or the height of its time currentcharacteristic is easily and accurately adjustable.

It is another object of the invention to provide a time-delay devicewhose time-current characteristic is not affected by temperature or thewear or inertia of mechanical parts.

It is still another object of the invention to provide a timing devicefor use with an electric system which accurately and quickly initiatesthe timing cycle upon the occurrence of a predetermined circuitcondition.

It is a still further object of the invention to provide a timing devicefor use with an electrical system that accurately determines when theproper timing period has elapsed.

It is yet another object of the invention to provide a timing devicewhich is rapidly reset after the disappearance of a fault regardless ofthe magnitude of the no fault current.

It is another object of the invention toprovide a time-delay devicewhich is relatively accurate at small .values of fault current.

These and other objects of the invention will become apparent from thedetailed description of the invention taken in view of the drawings inwhich:

FIG. 1 is a block diagram showing the major components of the instantinvention;

FIG. 2 is a circuit diagram of one embodiment of the invention;

FIGS. 3-6 and 11 are curves showing how the time currentcharacteristicof the device can be varied;

FIG. 7' is a circuit diagram of an alternate embodiment of the inventionembracing various modifications of the embodiment shown in FIG. 2;

FIGS. 8 and 9 are alternate embodiments of certain portions of theinstant invention; I

FIG. 10 shows a schematically illustrated repeating circuit interrupterhaving a time delay device according to the invention; and

FIG. 12 is a block diagram showing how the instant invention canbemodified for use with a three phase system.

FIG. 1 is a block diagram showing the major components of a time-currentrelay according to the invention and includes a timing portion 10, aminimum actuation current sensing portion 12 and a condition sensing andactuation portion 14. If the device is to be used in a circuitinterrupter or recloser, it is coupled to the system to be protected 20by means of a current transformer 22, a bridge type rectifier 24, and acurrent transformer shunting switch 26. When coupling switch 26 isopened the input of the timing portion 10 receives a rectified currentproportional to the alternating current flowing in system 20. Theclosing of coupling switch 26 short circuits the secondary of currenttransfonner 22, and, in effect, uncouples the time delay device from thesystem 20.

In general terms the timing portion comprises means operable upon theoccurrence of a predetermined circuit condition to begin timing thecondition as a function of its magnitude. This is accomplished byintegrating the condition so that the timing cycle comprises the periodrequired for this integral to reach a predetermined value.

' More specifically this portion includes a first energy storage meanscoupled to rectifier 24 and adapted, under certain conditions ofoperation, to be charged by the rectified secondary current fromtransformer 22. The time required for this energy storage means toachieve a predetermined energy level for any given'current in system 20determines the time current characteristic of the device. Thischaracteristic may be modified by utilizing impedances in circuit withthe first energy storage means. A second energy storage means may alsobe coupled to the rectifier 24 so that energy may be stored therein toprovided operating power for the other portions of the device.

The minimum actuation current sensing portion 12 includes means forsensing the occurrence of the predetermined circuit condition andthereupon initiating the integrating cycle of the timing portion 10.This portion is connected to the rectifier 24 and to the timing portion10 and is operative to prevent the storage of energy on the first energystorage means until the magnitude of the current in the secondary ofcurrent transformer 22 indicates the occurrence of said predeterminedcircuit condition. Upon this event the first energy storage means isallowed to charge up. The condition sensing and actuation portion 14comprises means for determining when the condition integral reaches apredetermined value and includes condition sensitive means coupled tosaid first energy storage means and operable when the energy storedtherein reaches a predetermined level.

In the embodiment of the invention shown in FIG. 2, the first and secondenergy storage means of the phase timing portion 10 comprise a timingcapacitor 29 and a power supply capacitor 30 and each is associated withcurrent dividing charging circuits so that they may be coupled to thesecondary of current transformer 22. These charging circuits include afirst charging resistor 32 in series with positive input terminal 34 anda second charging resistor 36 and the emitter-base circuit of a chargingtransistor 40 which are connected in series with each other and inparallel with the first charging resistor 32 so that a current splitwill result therebetween. The positive power supply terminal A of powersupply capacitor 30 is connected to the junction of the first chargingresistor 32 and the base of charging transistor 40 and the negativepower supply terminal B thereof is connected to the negative inputterminal 42 so that the current flowing in resistor 32 will charge thepower supply capacitor 30. One end of timing capacitor 29, on the otherhand, is connected to the collector of charging transistor 40 and theother end thereof is connected to the negative input terminal 42 so thatit will be charged by the current flowing in charging resistor 36, sincethe emitter and collector currents of charging transistor 40 aresubstantially equal. It will be appreciated, that by making chargingresistor 36 relatively larger than charging resistor 32, a largerportion of the input current will flow to the power supply capacitor 30than will flow in the charging circuit of timing capacitor 29, therebyallowing the latter to be smaller, and hence more sensitive, than wouldbe the case if there was a substantially equal current split.

In order to limit the charge stored on power supply capacitor 30, aby-pass circuit consisting of transistor 44 and Zener diode 45 areprovided. The emitter of transistor 44 is connected to the positivepower supply terminal A, the collector thereof is directly connected tothe negative power supply terminal B, and its base is connected to thelatter through Zener diode 45. In operation, when coupling switch 26 isopened, charge will be stored on capacitor 30 until its voltage, whichis also the emitter-base voltage of transistor 44, exceeds the breakdownpotential of Zener diode 45, whereupon the excess charge on capacitor 30will begin to flow through the emitterbase circuit of transistor 44 andZ ner diode 45. In this manner, current not necessary to maintain powersupply capacitor 30 at its desired voltage, is by-passed throughtransistor 44 and Zener diode 45. I

The charging circuit of timing capacitor 29 includes a first variabletiming resistor 47 in series with said timing capacitor and connectedbetween its positive terminal C and the collector of transistor 40, anda second variable resistor 48 in a parallel circuit with respect to saidti ing capacitor. While in the embodiment of FIG. 2 the second variableresistor is connected to the collector of transistor 0, as will becomeapparent from the discussion of other bodiments, it may be connected toany point between the p sitive terminal C of timing capacitor 29 and theemitter of t nsistor 40. In order to prevent the discharge of timingcapacitor 29 through parallel connected timing resistor 48 a rec'tifier50 is connected between timing capacitor 29 and its p int of connectionwith said resistor which in FIG. 2 is betwee resistor 47 and thecollector of transistor 40.

Series connected timing resistor 47 and parallel connected timingresistor 48 perform the function of modifying the slope of thetime-current characteristic of the device. As will be more fullyexplained below, the time-delay device illustrated in FIG. 2 will bemade operative when the voltage at junction point D, between thecollector of transistor 40, rectifier 50 and timing resistor 48, reachesa predetermined value. It can be seen that this voltage comprises thesum of the voltage drop across timing resistor 47 and the voltage acrosstiming capacitor 29.

In order to illustrate how the timing resistors 47 and 48 operate tomodify the time-current characteristics of the device, reference is madeto FIGS. 3, 4, and 6 in which curve 52 represents the time-currentcharacteristic which the device illustrated in FIG. 2 would have ifresistors 47 and 48 were eliminated, that is, if resistor 47 were shortcircuited or had a value of zero resistance so that there would be novoltage drop across it, and if resistor 48 were open circuited or had avalue of infinite resistance so that it could not shunt current aroundtiming capacitor 29. In other words, curve 52 represents the timerequired for the current flowing in resistor 36 to charge timingcapacitor 29 to the predetermined energy level required for operation.It will be appreciated that timing capacitor 29 has an inversetime-current characteristic, that is, it charges up in a relativelyshort time at high current values while at low current values arelatively longer charging time is required.

The addition of timing resistor 47 will have little effect on thetime-current characteristic of the device at very low values of currentsuch as I in FIG. 3, because the voltage drop across this resistor,resulting from such low current values will be negligible compared tothe total voltage required for operation. As a result, the voltageacross timing capacitor 29, resulting from the accumulation of chargethereon, will comprise substantially all the voltage required foroperation. At higher values of current, however, such as I, in FIG. 3,the voltage drop across timing resistor 47 will be substantiallyincreased, and, accordingly, represent a significant portion of thetotal operating voltage. As a result, junction point D in FIG. 2 willreach the required operating voltage in a shorter time than thatrequired to charge timing capacitor 29 to this voltage value. The use oftiming resistor 47 will have the effect, therefore, of shortening theoperating time of the time current device for a current I, from a time Ton curve 52, which is the charging time of timing capacitor 29, to ashorter time T on curve 53. Similarly, an increase in the resistance oftiming resistor 47 will increase the voltage drop across it, therebyfurther shortening the operating time for current I, from time T: oncurve 53 to time T on curve 54. It can therefore be seen that by varyingtiming resistor 47 from zero through a range of finite values, a familyof time current characteristics can be obtained similar to curves 52, 53and 54 shown in FIG. 3.

Referring now to FIGS. 2 and 4, it can be seen that if the resistance oftiming resistor 48,were changed from infinity to some finite value,current would be shunted through it and around timing capacitor 29. As aresult, some of the current that would otherwise charge timing capacitor29 will be drained off, thereby lengthening the time required forcapacitor 29 to charge up to a predetermined voltage value. This effectwill be negligible at a very high current value, such as I, in FIG. 4,because the current drained off by timing-resistor 48 will be negligiblecompared to the total current flowing in the collector of transistor 40so that the current available to charge timing capacitor 29 will besubstantially all of this collector current. At relatively lower valuesof fault current, however, such as I in FIG. 4, the current drained offthrough timing resistor 48 becomes a substantial portion of the currentflowing in the collector of transistor 40 so that the time required fortiming capacitor 29 to charge up will be significantly increased. As aresult, by changing the resistance of timing resistor 48 from infinityto some finite value, the charging time of timing capacitor 29 willincrease from time F on curve 52 to a longer time T on curve 56.Similarly, a further decrease in the resistance of timing resistor 48will increase the amount of shunted current thereby further lengtheningthe time required for the charging of timing capacitor 29 by a current Ifrom time T on curve 56 to a longer time T on curve 57.

It can therefore be seen from FIGS. 3 and 4, that the slope of thetime-current characteristic of the device at high fault current valuescan be substantially modified by varying timing resistor 47 while at lowfault current values the slope thereof can be substantially modified byvarying timing resistor 48. As a result, by a suitable variation of bothtiming resistors 47 and 48 a family of time current characteristics,such as those represented by curves 52, 58 and 59 shown in FIG. 5, maybe obtained.

The time current characteristic of the device can be further varied bychanging the capacitance of timing capacitor 29 whereupon the timerequired for it to charge up will change accordingly. Such variationswill have the effect of moving the time-current characteristics of thedevice vertically, giving a family of time-current characteristics suchas curves 52, 62 and 61 in FIG. 6. Hence, by suitably varying timingcapacitor 29 and timing resistors 47 and 48 the time currentcharacteristic of the relay can be widely varied both as to slope andheight. As a result of this flexiblity, the time-current deviceaccording to the invention may be easily and accurately coordinated witha wide variety of secondary protective devices without modification orre-design.

In order to insure that the device will operate only upon the occurrenceof a predetermined fault in the system 20, the minimum actuation currentsensing portion 12 is provided with means for sensing the occurrence ofsaid fault and to then initiate the timing portion 10. More specificallythis portion is provided with means for shunting the timing capacitor 29during no fault conditions and means responsive to a predeterminedcurrent in said system to prevent the discharge of said timing capacitorthrough said shunting means upon the occurrence of a fault.

Referring again to FIG. 2, timing capacitor 29 is normally shunted byleakage resistor 63 through the path defined by conductor 65, rectifier66, conductor 68 and negative supply conductor 69. As a result of thisleakage through resistor 63, timing capacitor 29 is held to a negligiblevoltage with respect to that value necessary for operation of thedevice. In this manner the time-current relay is prevented fromoperating at currents below the desired minimum fault or actuationcurrent value.

The minimum actuation current of the device is sensed by comparing anelectrical signal which is proportional to the current in system withthe actuation value of a signal responsive device. When this actuationvalue is exceeded, the minimum actuation current sensing portion is madeoperative to prevent the further discharge of timing capacitor 29through leakage resistor 63. As a result, timing capacitor 29 commencescharging up, and the timing cycle begins.

The signal responsive device of the minimum actuation current sensingportion 12 comprises a transistor 70 whose base is connected to theinput terminal 34 through a coupling circuit so that said base receivesa voltage proportional to the current flowing in the secondary ofcurrent transformer 22. The emitter of transistor 70 is held at a fixedpotential by a Zener diode 72 and a resistor 73. When the minimumactuation current of the device is equalled or exceeded the basepotential of transistor 70 will exceed its emitter potential so that itwill conduct, whereupon, the minimum actuation current sensing portion12 becomes operative to prevent the further discharge of capacitor 29through leakage resistor 63.

The coupling circuit to the base of transistor 70 includes a firstcoupling transistor 75 and a second coupling transistor 76. The base ofthe first coupling transistor 75 is connected to the positive powersupply terminal A through positive supply conductor 77, while theemitter thereof is connected to input terminal 34 by conductor 78 andresistor 79. It can be seen that resistor 32 on the one hand andresistor 79 and the emitter-base circuit of transistor 75 on the otherare connected in parallel, and accordingly, the emitter of transistor 75will be at a higher potential than its base. As a result, collectorcurrent will flow from transistor 75 to the voltage divided consistingof resistor 80 and adjustable resistor 82, which are serially connectedbetween said collector and the negative power supply conductor 69. Thiscurrent will be proportional to the current in system 20 and accordinglythe potential of junction point B between resistors 80 and 82 will beproportional to this current. The base of the second coupling transistor76 is connected to junction point E while its emitter is connected tothe negative supply conductor 69 through resistor 84 and its collectoris connected to the positive power supply conductor 77 through resistor86. The voltage on the base of coupling transistor 76, which isproportional to the current in system 20, determines the magnitude ofits emitter and collector currents. It can be seen, therefore, that thepotential of junction point F, between the emitter of transistor 76 andresistor 84, will also be proportional to the system current since it isdetermined by the voltage drop across resistor 82 and hence, isproportional to the emitter current of transistor 76. The base of signalresponsive transistor 70 is connected to junction point F and itsemitter is connected to junction point G between Zener diode 72 andresistor 73. The other terminals of Zener diode 72 and resistor 73 areconnected to the negative supply conductor 69 and the positive supplyconductor 77, respectively. When the system is initially energized,resistor 73 will hold junction point G at the potential of positivepower supply terminal A until this potential exceeds the breakdownpotential of Zener diode 72 whereupon it will begin conducting andjunction point G will thereafter be held at this potential.

Because signal responsive transistor 70 is of the N.P.N. type, it willconduct when its base potential exceeds its emitter potential, and hencewhen the potential of junction point F exceeds the potential of junctionpoint G. It will be recalled that the potential of junction point F isproportional to the potential of junction point E and that the voltageof the latter is the function of the voltage drop across variableresistor 82. Hence, by adjustment of variable resistor 82, the voltageof junction point F can be made to exceed the breakdown potential ofZener diode 72 and, as a result, the potential of junction point G, atany desired value of current in system 20. By properly setting resistor82, therefore, transistor 70 can be made operative at any predeterminedvalue of system current which is then the minimum actuation current ofthe time delay device. Any current equal to or above this minimumactuation current is considered a fault current and will cause thedevice to operate.

The collector of signal responsive transistor 70 is connected to thenegative power supply conductor 69 through capacitor 88 and to thepositive power supply conductor 77 through serially connected resistors90 and 92. The base of an output transistor 94 is connected to junctionpoint H between resistors 90 and 92 while its emitter is connected topositive power supply conductor 77 and its collector is connected tojunction point J between conductor 68 and leakage resistor 63.Before'signal responsive transistor 70 begins conducting, resistor 92will hold junction point H at the same potential as the emitter ofoutput transistor 94 so that said transistor will not conduct. Whensignal responsive transistor 70 begins conducting as a result of afault, however, collector current will flow from the positive powersupply conductor 77 through resistors 92 and 90. The resulting voltagedrop across resistor 92 lowers the potential of junction point B, andhence the base of output transistor 94 relativeto its emitter potentialwhereupon said transistor will begin conducting collector current tojunction point J. The collector current from output transistor 94 flowsthrough leakage resistor 63 raising the potential of junction point J tosome positive value. Capacitor 88 performs the function of holdingjunction point K at a substantially constant value after transistor 70begins conducting so that transistor 70 will continue to conduct eventhough the power supply is a pulsating DC which periodically goesthrough zero.

It will be recalled that timing capacitor 29 has been dischargingthrough resistor 63 during the period of no-fault operation, so that thepotential at its positive terminal C will be less than the potentialthat junction point J assumes as a result of the current flowing throughthe collector of coupling transistor 94 upon the occurrence of a fault.This difference in potential between points C and J, prevents thefurther discharge of timing capacitor 29 through resistor 63, whilerectifier 66 prevents reverse current flow from junction point J toterminal point C. Since timing capacitor 29 can not longer dischargethrough resistor 63 it begins charging and continues until its voltage,plus the voltage drop across resistor 47 is sufficient to causeoperation of the energy sensing and actuation portion 14 of the devicein the manner described in the ensuing paragraphs.

The condition sensing and actuation portion 14 is operative to compare avoltage proportional to the voltage at junction point D with a fixedreference voltage. When this proportional voltage exceeds the referencevoltage a voltage comparison transistor 98 begins conducting whereuponthe actuation portion becomes operative.

The voltage comparison transistor 98 is coupled to junction point D bycoupling transistors 100 and 101, which are cascaded as emitterfollowers to reduce to a very small value the current drawn from thetiming portion 10. Each of the coupling transistors 100 and 101 is ofthe NPN type and the collector of each is connected to the positivepower supply terminal A, while the base of transistor 100 is connectedto junction point D and its emitter is connected to the negative powersupply terminal B through resistor 103. In a like manner, the base oftransistor 101 is connected to the emitter of transistor 100 and theemitter thereof is connected to the negative power supply terminal Bthrough a voltage divider consisting of variable resistors 105 and 106which are joined at junction point M. Because the base of couplingtransistor 100 is connected to junction point D and because the emitterthereof is connected to the negative power supply terminal B throughresistor 103 its base potential will exceed its emitter potential andemitter current will flow through resistor 103. The emitter current fromcoupling transistor 100 flowing through resistor 103 will, in turn,raise the potential of junction point L between resistor 103 and theemitter and base of transistors 100 and 101 respectively, to somepositive potential which is proportional to the potential at junctionpoint D and which is higher than the emitter potential of transistor101. This results in a transistor 101 emitter current flowing throughresistors 105 and 106, and this current is also proportional to thevoltage at junction point D. The resulting voltage drops in resistors105 and 106 places a potential on junction point M which is proportionalto the potential at junction point D.

The base of voltage comparing transistor 98 is connected to junctionpoint M so that its base voltage is proportional to the voltage atjunction point D.

The emitter of voltage comparing transistor 98 is connected to thejunction point P between Zener diode 110 and resistor 111 whose otherterminals are connected to the negative power supply terminal B and tothe positive power supply terminal A respectively. When coupling switch26 is initially opened, resistor 111 will hold junction point P at thepotential of the positive power supply terminal A until this potentialexceeds the breakdown potential of Zener diode 110. The potential ofpoint P is, thereafter, held at the breakdown potential of Zener diode110 and, as a result, the emitter of voltage comparing transistor 98will be held at this fixed potential.

Because voltage comparing transistor 98 is of the NPN type it willconduct only when its base potential exceeds its emitter potential.Hence, when the potential at junction point M is less than the breakdownpotential of Zener diode 110, the voltage comparing transistor 98 willbe non-conducting. Resistor 105 is made adjustable so that when junctionpoint D reaches the potential at which it is desired to operate thecondition sensing portion 14, the voltage at point M can be made justsufficient to cause voltage comparing transistor 98 to begin conducting.

A relay winding 120 is connected between the collector of voltagecomparing transistor 98 and the positive power supply terminal A so thatwhen said transistor begins conducting as the result of a fault in themanner discussed above, current will be drawn through relay winding 120.

Capacitor 122 holds the collector of transistor 98 at a sub stantiallyconstant potential even though the power supply is a pulsating DC. Thisallows transistor 98 to conduct steadily after its operation isinitiated so that relay 120 will not chatter.

It is understood that the energization of relay winding 120 can beutilized to actuate any apparatus with which the time delay deviceaccording to the invention is to be utilized. For example, it can bemade operative to close normally open contacts 124 thereby placing thetrip coil 126 of a circuit breaker across a suitable source ofelectrical energy, such as battery 128, whereupon the circuit breakersmain contacts 130 are tripped open thereby interrupting the current insystem 20.

In summary of the operation of the time delay device shown in FIG. 2,the current flowing in the collector of charging transistor 40 willsplit between the parallel paths defined by charging resistor 48 and theseries combination of timing resistor 47 and timing capacitor 29. Underno-fault conditions, capacitor 29 is prevented from charging because itis shunted by leakage resistor 63 which under such conditions, shuntssubstantially all the current flowing to said timing capacitor.

The current flowing in conductor 78 to the emitter of couplingtransistor 75 is proportional to the current in system 20 and it causesa transistor 75 collector current to flow through resistors 80 and 82thereby raising the potential of junction point E to a value which isalso proportional to said system current. Similarly, a transistor 76emitter current, which is controlled by the potential of junction pointE, flows through resistor 84 and raises the potential of junction pointF to a value proportional to the system 20 current. The base of signalcomparing transistor 70 is connected to junction point F while itsemitter is connected to junction point G which is held at a fixedpotential by Zener diode 72 and resistor 73. As a result, when thecurrent flowing in system 20 equals or exceeds the desired minimumactuating current of the device, the base voltage of voltage comparingtransistor 70 will exceed its emitter voltage and collector current willbegin flowing therein to the base of output transistor 94. Upon thelatter event, the base potential of output transistor 94 will fall belowits emitter potential whereupon collector current will begin flowing toleakage resistor 63. This, in turn, raises the potential of junctionpoint J so that timing capacitor 29 is thereafter prevented fromdischarging through leakage resistor 63 and it therefore beginscharging. As timing capacitor 29 charges up, the voltage at junctionpoint D will begin rising and the emitter currents flowing in couplingtransistors and 101, and which are proportional to the voltage atjunction point D will similarly rise. The potential of junction point M,resulting from the transistor 101 collector current will therefore alsofollow the potential of junction point D. The base of transistor 98which is coupled to junction point M will, therefore, always be at apotential proportional to the potential at junction point D while itsemitter will be held at a constant potential by Zener diode and resistor111. After timing capacitor 29 has charged for a predetermined time,which is the time delay of the device, the potential of junction point Mwill exceed the potential of junction point P and transistor 98 willconduct current to relay winding which, in turn, closes contacts 124 andthe device is thereby operated.

After the fault in system 20 has been interrupted, the potential atjunction point F will fall below that of junction point G and transistor70, and hence, transistor 94 will cease conducting. This allows thepotential at junction point J to fall below that of terminal C so thattiming capacitor 29 can again discharge through leakage resistor 63.This in turn lowers the voltage at junction point D and, consequently,at junction point M so that transistor 98 will cease conducting andrelay 120 is deactuated. The time necessary for timing capacitor 29 tosubstantially discharge through resistor 63 is the resetting time of thedevice, and this time is generally measured in terms of fractions of asecond. If the fault disappears while timing capacitor 29 is chargingbut prior to the attainment of the predetermined operating voltage atjunction point D, and hence prior to the energization of relay 120,timing capacitor 29 will similarly begin discharging through leakageresistor 63 and the device will reset.

FIG. 7 illustrated a number of ways in which the embodiment shown inFIG. 2 may be modified to achieve greater sensitivity, it beingunderstood that the invention contemplates the incorporation of thesemodifications into the circuit of FIG. 2 individually as well ascollectively as is done in FIG. 7.

It was found that increased accuracy can be achieved by utilizing NPNtype transistors for the charging transistor 40 and coupling transistor75 in the timing portion 12 and the energy sensing portions 14respectively, instead of the PNP type transistors shown in FIG. 2because the former type have smaller leakage currents. Because of thechanges in these two transistors it is also necessary to change thetypes of all other transistors and to reverse the polarity of thevarious rectifiers, and Zener diodes.

A second modification comprises the elimination of the power supplycapacitor 30 and its by-pass circuit comprising transistor 44 and Zenerdiode 45. The operating power is supplied entirely by battery 128through power supply terminals A and B. This modification necessitatesmoving the return path of the current flowing through charging resistor32 from the negative terminal B of power supply capacitor 30 in FIG. 2to the junction of resistor 32 and the base of charging transistor 40.As a result, the input terminals 34' and 42' of the time delay deviceare now disposed on either side of charging resistor 32. Timingcapacitor 29 is charged in the same manner as was previously discussedwith respect to FIG. 2 except, of course, that the direction of positivecurrent flow is reversed, and flows in FIG. 7 from timing capacitor 29through resistor 47, rectifier 50 and the collector-emitter circuit ofcharging transistor 40 and then through charging resistor 36.

Referring again to FIG. 2, it can be seen that although the currentflowing through resistor 63, as a result of discharge of timingcapacitor 29 therethrough, is negligible, a very small voltage drop willnonetheless exist thereacross. It will be recalled that under nofaultconditions, the voltage at terminal C will be equal to the potential atjunction point J. As a result of the voltage drop across leakageresistor 63 therefore, the potential at terminal C will be some positivevalue so that the discharge of timing capacitor 29 will not be entirelycomplete and a slight reduction in the charging time of capacitor 29 isthereby introduced. The percentage error introduced in the charging timeis a function of the ratio of the initial potential on terminal C, as aresult of the leakage current, to the final potential on said terminalwhen the device operates, i.e., the voltage across capacitor 29 when thepotential at junction point D is sufficient to cause voltage comparingtransistor 98 to conduct. This error will be insignificant at very smallvalues of fault current because under such circumstances the voltageacross timing capacitor 29 will be substantially the total potential atjunction point D and hence the potential of terminal C will be quitelarge. However, at very high values of fault current, where the voltagedrop across resistor 47 is a substantial portion of the final potentialat junction point D, the final potential at terminal point C issubstantially reduced and the initial potential at this point becomessignificant. It is to be remembered, however, that this error willmerely shorten the time required for timing capacitor 29 to charge sothat its only effect is to move the high current end of the time currentcharacteristic downward somewhat. This effect is eliminated in theembodiment in FIG. 7, however, by placing a small voltage biasing means140 between leakage resistor 63 and negative power supply conductor 69and also by shunting the timing capacitor 29 by a rectifier 142. Thismodification serves to hold the potential of terminal C at the potentialof power supply terminal B.

Assume for the sake of illustration, that the potential of power supplyterminal A in FIG. 7 with respect to ground is some negative value andthe potential of supply terminal B is zero or at ground potential, andassume further that biasing means 140 holds the terminal S of leakageresistor 63 at some small positive value with respect to ground. Becauseof the negative current which flows around timing capacitor 29 andthrough conductor 65 under no-fault conditions, a voltage rise willoccur across leakage resistor 63. The size of biasing means 140 is sochosen that it will hold terminal S of leakage resistor 63 at a positivepotential that is greater than the voltage rise across leakage resistor63. In this manner the voltage rise across leakage resistor 63 isentirely cancelled and junction point .I is held at a very small valueof positive potential that is the difference between the potential atjunction point S and said voltage rise. This small positive potential onjunction point J tends to drive positive current to terminal C, but thisterminal is grounded with respect to positive current by rectifier 142so that junction point C remains at zero potential. Rectifier 142 doesnot, however, pass the charging current in the collector of chargingtransistor 40 because, it will be recalled that in FIG. 7 this is anegative current. It can be seen, therefore, that voltage biasing means140 and diode 142 hold junction point C at zero potential regardless ofthe magnitude of the leakage current through leakage resistor 63.

It will be recalled from the discussion of FIG. 2, that at very highvalues of fault current, timing resistor 48 shunts only a small portionof the total charging current in the collector of transistor 40 while atvery low values of fault current, the current flowing through resistor48 is a very large proportion of said charging current. As a result, atvery low fault current values, only a very small quantity of currentwill be available to charge timing capacitor 29. This current is furtherdiminished by a small leakage current around capacitor 29 itself andalso through the input transistor of the voltage sensing portion14.'Also, in the circuit shown in FIG. 2 the current shunted throughtiming resistor 48 is proportional to the voltage across timingcapacitor 29. Hence, when timing capacitor begins charging as a resultof a fault the voltage across it will be substantially zero and hencealmost no current will flow through timing resistor 48. This, of course,will be true regardless of the size of this resistor. On the other hand,when the voltage across timing capacitor reaches a maximum, just priorto operation, the current shunted through timing resistor 48 will be ata maximum and its value will be governed by the size of this resistance.As a result, in the embodiment of FIG. 2, timing resistor 48substantially reduces the charging current only during the latterportion of the timing cycle. It can be seen, therefore, that at very lowvalues of fault current, where the timing capacitor 29 charging currentis quite small, the time delay of the device cannot be varied through awide range of values by variation of timing resistor 48. Thisshortcoming can be alleviated by fixing the magnitude of the currentwhich is shunted through timing resistor 48 to some arbitrary fixedvalue. By keeping this shunted current at a substantially constant valuefor the major portion of timing cycle, a wider range of charging timescan be obtained than where the charging current varies all during thecharging cycle. This is accomplished in the modification shown in FIG. 7by connecting timing resistor 48' to terminal C through rectifier 150and the emitter-collector circuit of transistor 152. The base oftransistor 152 is connected to junction point P, which, it will berecalled, is held at a fixed potential by Zener diode and resistor 11 1.Upon the occurrence of a fault, therefore, collector current will beginflowing in transistor 152 when the potential at terminal C reaches thepotential of junction point P, whereupon, a portion of the transistor 40collector current will begin shunting through the emitter and collectorcircuit of transistor 152 and through resistor 48'. This shunted currentwill be of such magnitude that the IR drop across resistor 48' is equalto the breakdown voltage of Zener diode 110. The current flowing throughtiming resistor 48' will, of course, vary as variations are made in theresistance thereof but for any given setting of said resistor, thecurrent shunted therethrough will have a fixed value. The purpose ofrectifier is to prevent timing capacitor 29 from being charged as aresult of the potential at junction point P. The latter modificationalso illustrates that the connection for timing resistor 48' can be madeeither to terminal C or to junction point D as in FIG. 2, as long asthis resistor is in a parallel circuit with respect to timing capacitor29.

FIG. 8 shows another embodiment of the timing portion 10 wherein thecurrent shunted through timing resistor 48' will have a fixed value forany given setting thereof. Here timing resistor 48" placed betweenemitter 40 and input terminal 42 so that the current available to chargetiming capacitor 29 can be reduced by a fixed value depending upon thesetting of said timing resistor.

In order to insure tripping power in the event that battery 128 shouldfail the energy sensing and actuation portion 14 of the device may bemodified as shown in FIG. 9 to include a second power supply capacitor160 connected in parallel to the first power supply capacitor 30 througha first rectifier 163 and to the battery 128 through a second rectifier162. Under normal conditions, the second power supply capacitor 160 ismaintained in a fully charged condition by battery 128 through rectifier162 which prevents the short circuiting of capacitor 160 should a faultoccur within the battery 128, while rectifier 163 prevents the firstpower supply capacitor 30 and the other circuit components from drawingbattery current. Should battery 138 fail, the second power supplycapacitor 160 will be charged by the rectified secondary current ofcurrent transformer 22 in the same manner as the first power supplycapacitor 30. In either event, the second power supply capacitor 160furnishes tripping power to the trip coil 126 and operation thereofwould be the same as discussed previously with respect to FIG. 2. If thebattery fails, however, and a fault current occurs while the secondpower supply capacitor 152 is without charge, the device will notoperate until said capacitor becomes charged. This will only affect thetime-current characteristics of the device at low values of faultcurrent wherein a fast tripping time is desired because the chargingtime of second power supply capacitor 160 may, under such circumstances,be slower than that of the time delay capacitor 29.

FIG. illustrates how the time delay device shown in FIG. 2 may beincorporated into a repeating circuit interrupter having reclosing means170, operation counting means 172 and lockout means 174. These portionsof a conventional repeating circuit interrupter are well known in theart and the specific details thereof form no part of the instantinvention, and therefore, are merely schematically illustrated in FIG.10 for the sake of simplicity. The minimum actuation current sensingportion 12 has been omitted from FIG. 10, but it will be understood thatit is identical with that shown in FIG. 2.

The reclosing means 170 is operable after a time delay to reclose themain contacts 130 after each opening operation thereof. The operationcounting means 172 is operable to initiate time delayed openingoperation of contacts 130 after they have executed a predeterminednumber of rapid opening operations. The operation counting means 172 isfurther operable to actuate lockout means 174 after a predeterminednumber of such time delayed operations so that the main contacts 130will be prevented from reclosing until the device is manually reset.

Reclosing means 170 includes a reclosing solenoid coil 176 operable uponbeing energized to pull the main contacts operating bar 178 upwardly asviewed in FIG. 10 to close the main contacts 130. Upon the opening ofmain contacts 130 the reclosing solenoid coil 176 is connectable acrossbattery 128 by conductors 180, 181 and 182, normally closed contacts 186and normally open contacts 188 in a manner to be discussed in theensuing paragraphs. It can be seen, however, that when the primarycontacts are closed as shown in FIG. 10, normally open contacts 188 holdsolenoid coil 176 deenergized.

It will be recalled that upon the occurrence of a fault relay winding120 is energized to close contacts 124 thereby placing trip coil 126across battery 128. Upon this event, trip plunger 190 is moved to theright in FIG. 10, rotating bell crank latch 191 in a counter-clockwisedirection about its pivot point 192 and against the force of its biasingspring 193 thereby releasing the main contacts operating bar 178 so thatit may move downwardly toward open position under the influence ofopening spring 194. When the main contacts operating bar 178 reaches itsfully open position, normally open contacts 188 will be closed byoperating arm 196 carried on said operating bar so that the circuitthrough solenoid coil 176 will be completed. This actuates reclosingsolenoid 176 to move operating bar 178 upwardly, thereby closing maincontacts 130. In order to allow fuses in the branch lines to coolproperly, instantaneous reclosing of main contacts 130 may be preventedby dash pot means 199 connected to operating bar 178.

It will be also recalled, that while the main contacts 130 are in theiropen position, relay winding was de-energized and contacts 124 areopened, so that trip coil 126 is also de-energized and bell crank latch191 is free to rotate in a clockwise direction under the influence ofbiasing spring 193 to its latched position shown in FIG. 10. As aresult, when operating bar 178 reaches its fully closed position asshown in FIG. 10 it will be latched in this position by bell crank latch191. If the fault disappears from system 20 while contacts were in theiropen position, they will remain latched upon reclosing. However, shouldthe fault persist main contacts 130 will again be tripped open andreclosed in the manner previously described. This cycling will continueuntil the fault clears or until lockout means 174 is actuated to lockthe main contacts open in the manner to be discussed herein below.

The operation counting means schematically illustrated in FIG. 10 is ofthe hydraulic type and utilizes as a hydraulic medium the dielectricfluid in which such repeating circuit interrupters are normallydisposed. This operation counting means includes a pump piston 198disposed in a pump cylinder 200 and a counting piston 202 disposed incounting cylinder 203. The pump piston 198 is driven by movement ofoperating bar 178 to which it is connected by means of a link 204 and abell crank 206 which is pivoted at 207 and which is connected at one endto link 204 and at its other to operating arm 208 mounted on theoperating bar 178. Each time the main contacts 130 are opened, bellcrank 206 is rotated about pivot 207 in a clockwise direction so thatpump piston 198 is moved upwardly drawing hydraulic fluid into pumpcylinder 200. When contacts 130 are reclosed, bell crank 206 is rotatedin a counter-clockwise direction to force a fixed quantity of hydraulicfluid from pump cylinder 200 through passage 210, and past ball check212 to the pressure side of counting piston 202. As the circuitinterrupter operates repeatedly, the piston 202 is forced hydraulicallyupward in a step by step manner causing a corresponding movement oftiming bar 214 to the left, as viewed in FIG. 10, through the agency oflink 216 and bell crank 218. Upward movement of counting piston 202rotates bell crank 218 in a counter clockwise direction about pivot 219,to force timing bar 214 to the left against the influence of resettingspring 220. After lockout, or after the fault was cleared prior tolockout, the leakage of hydraulic fluid past counting piston 202 allowsresetting spring 220 to return timing bar 214 and timing piston 202 totheir initial positions shown in FIG. 10.

Movement of timing bar 214 a predetermined distance to the left after apredetermined number of opening operations operates to modify the valuesof the primary timing capacitor 29 and the primary timing resistors 47and 48 by placing in circuit with these timing impedances a second setof auxiliary timing impedances comprising capacitor 229 and resistors247 and 248. This alters the time delay characteristics of the timedelay device in the manner discussed with respect to FIGS. 3-6, so thatafter a predetermined number of opening operations, the circuitinterrupter is automatically switched from one time currentcharacteristic to another. Modification of the values of the primarytiming impedances is accomplished by switch means 222 which is actuableby timing bar 214 after a predetermined number of operations to coupleor uncouple the auxiliary timing impedances to or from the primarytiming impedances.

Movement of timing bar 214 is transmitted to switch means 222 bypositioning pins 223, 223' and 223" which act as stop means to preventthe counter-clockwise rotation of switch carriers, 224, 224' and 224"around their respective pivots 225, 225 and 225" under the influence oftheir associated biasing springs 226, 226' and 226". Each of the contactmembers 224, 224 and 224" carries a conductive brush member 227, 227 and227" respectively which may be manually set in one of two angularpositions against stops 228-230, 228'230 and 228230". For the sake ofillustration, brush contact 227 and 227' are shown in a first angularposition relative to fixed contacts 232 and 232 and against stop members228 and 228 respectively while brush contact 227" is shown in a secondangular position against stop member 230", so that it will engage fixedcontact 232' Assume, for the sake of illustration, that the repeatingcircuit interrupter schematically illustrated in FIG. is designed toexecute two rapid opening operations and two time delayed operationsprior to lockout. Upon the first reclosing operation, timing bar 214will be moved a first predetermined distance to the left as viewed inFIG. 10 allowing contact members 224, 224' and 224" to rotate through asmall counter-clockwise angle. This moves conductive brush members 227and 227' a short distance toward the left hand edge of stationarycontacts 232 and 232' respectively and also moves conductive brush 227"to the right band edge of stationary contact 232". Upon the movement oftiming bar 214 a second predetermined distance to the left when the maincontacts 130 are reclosed for a second time, the brush members 227 and227' will be moved onto their associated stationary contacts 232 and 232while brush member 227" will be moved off of its associated stationarycontact 232". This completes the circuit through conductors 250 and 251to place auxiliary timing capacitor 229 in parallel with primarycapacitor 29 and also completes the circuit through conductors 253 and254 to place auxiliary timing resistor 248 in parallel with primarytiming resistor 48. On the other hand, movement of conductive brush 227"off of stationary contact 232 interrupts the circuit through conductors256 and 257 to take auxiliary timing resistor 247 out of parallelismwith primary timing resistor 47.

It will be appreciated by those skilled in the art that the placing ofauxiliary timing capacitor 229 in parallel with primary timing capacitor29 increases the total timing capacitance thereby moving the time delaycharacteristic of the device vertically as shown in FIG. 6 from curve 62to curve 61. The magnitude of this shift will, of course, depend on therelative sizes of primary timing capacitor 29 and auxiliary timingcapacitor 229. For example, if primary timing capacitor 29 has a valueof zero capacitance and auxiliary timing capacitor 229 has some finitevalue of capacitance, the initial opening operations will besubstantially instantaneous while subsequent opening operations will betime delayed in accordance with the value of auxiliary timing capacitor229.

In a similar manner, the placing of auxiliary timing resistor 248 inparallel with primary timing resistor 48 will have the effect ofdecreasing the total resistance shunting the timing capacitor andthereby increasing the slope of the time current characteristic at itshigh current end as discussed with respect to FIG. 3. On the other hand,the open circuiting of auxiliary timing resistor 247 removes it fromparallelism with timing resistor 47 thereby increasing the resistance inseries with the timing capacitor so that the slope at the low currentend of the time current characteristic is increased in the mannerdiscussed with respect to FIG. 4.

It can be seen, therefore, that by increasing the capacitance of thetiming capacitor and the resistance of the series timing resistor and bydecreasing the resistance of the parallel timing resistor after apredetermined number of opening operations, the time currentcharacteristic for subsequent operations may be given a steeper slope aswell as moved vertically. This is illustrated in FIG. 11 wherein 260represents the time current characteristic of the device during theinitial or rapid opening operations and 262 represents its time currentcharacteristic during time delayed operations. It will be understoodthat the slope of the time delayed curve 262 may be decreased relativeto the rapid curve 260 by reversing the positions of conductive brushes227 and 227" from that shown in FIG. 10 so that conductive brush 227intially engages stationary contact 232 and conductive brush 227 isinitially out of engagement with its associated stationary contact 232".Those skilled in the art will further appreciate that the degree ofslope for the rapid and time delayed curves can be altered by suitableadjustment of primary and auxiliary timing resistors 47, 48, 247 and248.

After a predetermined number of opening operations, usually four, thefault is considered permanent and it is then desirable to prevent themain contacts from subsequently reclosing. This is accomplished in theembodiment illustrated in FIG. 10 by operating lockout means 174 to opennormally closed contacts 186 so that the closing of normally opencontacts 188 will not result in the energization of reclosing solenoidcoil 176. This is accomplished by providing an operating arm 260 ontiming bar 214 which is so located relative to lockout means 174 thatafter three reclosing operations it is moved sufficiently to the left inFIG. 10 to engage the upper end of latch lever 262 and rotate it in acounter-clockwise direction against the force of biasing spring 263. Aslatch lever 262 rotates its lower end 264 moves past the upper end 265of switch operating lever 266 so that the latter is then free to rotatein a counter-clockwise direction under the influence of its associatedbiasing spring 268 until it engages stop 270. This snaps normally closedcontacts 186 open and thereby prevents the re-energization of reclosingsolenoid 176 upon the subsequent opening of main contacts 130. After themain contacts 130 have been locked open in this manner counting piston202 will resettle in counting cylinder 203 under the influence ofbiasing spring 220. Contacts 186 may be reclosed by rotating operatinglever 266 in a clockwise direction in any suitable manner such as bycoupling it to a manual operating handle (not shown). Such rotationmoves the upper end 265 of operating lever 266 past the lower end 264 oflatch lever 262 so that it is again latched in the position shown inFIG. 10.

FIG. 12 illustrates how the time delay device according to the inventionmay be modified for use in a three phase system. Such modificationincludes the provision of a phase timing portion 10, 10' and 10" foreach of the phases of the system, and each is coupled to its respectivephase conductor, 20, 20' and 20" by means of an individual currenttransformer 22, 22' and 22" and their associated bridge type rectifiers24, 24 and 24". Conductors 78, 78' and 78" connect each of thecorresponding current transformers to a single minimum actuation currentsensing portion 12 through isolating rectifiers 280, 280' and 280 whichperform the function of preventing current flow between the variousoutput circuits of the bridge type rectifiers 24, 24' and 24". As aresult, terminal point T between conductors 78, 78' and 78" will be at apotential which is equal to the highest potential across any of thethree input terminals of phase timing portions l0, l0 and 10". Thisinsures that the minimum actuation current sensing portion 12 will beactuated when a fault current occurs in any of the three phases 20, 20'and 20". Junction points D, D and D of phase timing portions 10, 10 and10", respectively, are coupled to the input of the energy sensing andactuation current portion 14 through isolating rectifiers 282, 282' and282" which prevent the flow of current between said timing portions.

Assume for the sake of illustration, that a fault occurs in phase 20'.This will result in an increased current to appear in conductor 78raising the potential at junction point T to a value which prevents thefurther leakage of the charging current around the timing capacitorsassociated with each of the phase timing portions l0, l0 and 10" andthrough their respective conductors 65, 65 and 65". As a result, each ofsaid timing capacitors will begin charging. However, the timingcapacitor associated with phase timing portion 10 will become charged toits operating potential first because the fault current in phase 20'results in a higher charging current thereto. As a result, its junctionpoint D will reach the operating potential before junction points D andD", and it will cause the operation of energy sensing and actuationportion 14 in the manner heretofore discussed with respect to a singlephase device.

it can be seen from the foregoing that the time delay device accordingto the invention allows the time current characteristic of the circuitinterrupter or other device with which it is associated to be easily andaccurately varied over a wide range of values and that the device can beadapted for use in both single and polyphase systems.

While only a few embodiments of the invention have been illustrated anddescribed herein, it is understood that a number of other modificationswill be apparent to those skilled in the art without departing from thetrue spirit of the invention, and accordingly, it is intended in theappended claims to cover all such modifications.

I claim as my invention: 7

1. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor coupled to saidinput and chargable by the current flowing therein, leakage resistormeans normally shunting said timing capacitor for preventing thecharging thereof by the current flowing to said input, normally inactiveelectronic circuit means coupled to said input and to said timingcapacitor and responsive to an abnormal circuit condition in said systemfor conducting current to said resistor means to modify the voltage dropthereacross and prevent the discharge of said capacitor through saidleakage resistor means upon the occurrence of said abnormal circuitcondition so that said timing capacitor may begin charging.

2. In an electronic timing device having an input adapted to beconnected to an electrical system, energy storage means coupled to saidinput, leakage resistor means nonnally shunting said energy storagemeans for preventing the charging thereof by the current flowing to saidinput, overload sensing means coupled to said input and normallyinactive electronic means coupled to said leakage resistor means, saidoverload sensing means being responsive to the current in said system toactuate said electronic circuit means for raising the voltage dropacross said leakage resistor means to thereby prevent the discharge ofsaid energy storage means therethrough when the current in said systemreaches a predetermined value, whereby said energy storage means isallowed to charge up.

3. In an electronic timing device having an input adapted to beconnected to an electrical system, timing capacitor means coupled tosaid input, leakage resistor means normally shunting said timingcapacitor for preventing the charging thereof by the current flowing tosaid input, circuit means including overload sensing means coupled tosaid input and normally inactive electronic means coupled to saidleakage resistor means, said overload sensing means being responsive tothe current in said system to actuate said electronic means to conductcurrent to said leakage resistor to raise the voltage drop thereacrossto thereby prevent the discharge of said timing capacitor meanstherethrough when the current in said system 7 reaches a predeterminedvalue, whereby said energy storage means is allowed to charge up, andmeans for preventing current from flowing from said leakage resistormeans to said timing capacitor means.

4. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor connected to saidinput and chargeable by the current flowing therein, a leakage resistorshunting said timing capacitor, voltage comparison means having sensingmeans and reference voltage means, said voltage comparison means alsohaving output means connected to said leakage resistor means, saidvoltage comparison means being actuable when the voltage at said sensingmeans exceeds said reference voltage to conduct current to said leakageresistor means, circuit means connecting said sensing means to saidinput for placing a voltage on said sensing means that is proportionalto the current at said input whereby output current will flow to saidleakage resistor when the current at said input exceeds a predeterminedvalue to thereby raise its voltage to a value higher than the voltageacross said timing capacitor so that the further discharge thereof isprevented, unidirectional circuit means for preventing current flow fromsaid leakage resistor means to said timing capacitor, and output meanscoupled to said timing capacitor and operable when the charge thereonexceeds a predetermined value.

5. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor connected to saidinput and chargeable by the current flowing therein, a leakage resistorshunting said timing capacitor, a signal responsive transistor,reference voltage means, circuit means connecting the base of saidsignal responsive transistor to said input for placing a potential onsaid base that is proportional to the current at said input, the emitterof said transistor being connected to said reference voltage meanswhereby collector current will flow in said transistor when the currentat said input exceeds a predetermined value, nonnally non-con ductingcurrent responsive means connected to said leakage resistor and to thecollector of said transistor so that when collector current flowstherein as a result of said predetermined current at said input saidcurrent responsive circuit means will conduct current to said leakageresistor to thereby raise its voltage to a value higher than the voltageacross said timing capacitor so that the further discharge thereof isprevented, and diode means for preventing current from flowing from saidleakage resistor to said timing capacitor.

6. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor connected to saidinput and chargeable by the current flowing therein, a leakage resistorshunting said timing capacitor, triode means having a source element, aload element and a control element, reference voltage means, circuitmeans connecting the control element of said triode meansto said inputfor placing a potential on said control element that is proportional tothe current at said input, the source element of said triode means beingconnected to said reference voltage means whereby load current will flowin said load element when the current at said input exceeds apredetermined value, normally non-conducting current responsive meansconnected to said leakage resistor and to said load element so that whenload current flows in said triode means as a result of saidpredetermined current at said input said current responsive means willconduct current to said leakage resistor to thereby raise its voltage toa value higher than the voltage across said timing capacitor so that thefurther discharge thereof is prevented, and output means coupled to saidtiming capacitor and operable when the charge thereon exceeds apredetermined value.

7. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor coupled to saidinput and chargeable by the current flowing therein, leakage resistormeans connected in parallel with said timing capacitor for normallyshunting said charging current therearound, voltage biasing meansconnected to said leakage resistor means in a sense opposite to thesense of said shunted current so that the efiect of the voltage dropacross said leakage resistor on the potential of the junction betweensaid leakage resistor and said timing capacitor is partially cancelled,rectifier means shunting said timing capacitor and operable to shuntaround said timing capacitor any reverse current from said leakageresistor as a result of said biasing means whereby the voltage drop insaid leakage resistor as a result of said leakage current does notproduce a difference in potential across said timing capacitor, circuitmeans coupled to said input and responsive to the current in said systemfor preventing the discharge of said capacitor through said leakageresistor means when the current in said system reaches a predeterminedvalue.

8. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor connected to saidinput and chargeable by the current flowing therein, a leakage resistorconnected in parallel with said timing capacitor for shunting saidcharging current therearound; means coupled to said timing capacitor andto said leakage resistor means for cancelling the effect of the shuntedcurrent produced voltage drop across said leakage resistor on saidtiming capacitor means whereby the voltage drop in said leakage resistordoes not produce a potential difference across said timing capacitor,voltage comparison means having sensing means and reference voltagemeans, said voltage comparison means also including output meansconnected to said leakage resistor means said voltage comparison meansbeing actuable when the voltage at said sensing means exceeds saidreference voltage to conduct current to said leakage resistor means,circuit means connecting said sensing means to said input for placing avoltage on said sensing means that is proportional to the current atsaid input whereby output current will flow to said leakage resistor tothereby raise its voltage to a value higher than the voltage across saidtiming capacitor so that the further discharge thereof is prevented.

9. In an electronic timing device the combination of an input adapted tobe connected to an electrical system, timing capacitor means connectedto said input and chargeable by the current flowing therein, animpedance in a parallel circuit with respect to said timing capacitormeans for shunting a portion of said current around said timingcapacitor said parallel circuit including means for holding said shuntedcurrent to a predetermined value, leakage means connected to saidcapacitor and normally preventing the charging thereof, said energyleakage means including circuit means connected to said input andresponsive to a predetermined current in said system for preventing theleakage of said current means through said leakage means so that saidtiming capacitor means beings charging upon the occurrence of saidpredetermined current.

10. in an electronic timing device the combination of a pair of inputterminals, a first charging resistor having one end connected to one ofsaid input terminals, a second charging resistor and a transistor, saidsecond resistor and the emitterbase circuit of said transistor beingconnected in parallel with said first charging resistor, a first energystorage means between the other end of said first resistor and the otherinput terminal, a second energy storage means connected between thecollector of said transistor and said other input terminal, whereby eachof said energy storage means is chargeable by the current flowing in itsassociated resistor, energy responsive means coupled to said firstenergy storage means and responsive to the energy stored therein foractuation when the energy on said first energy storage means reaches apredetermined value, said second energy storage means being connected tosaid energy responsive means for supplying operating energy thereto.

11. In a device for protecting an electrical system, the combination ofa pair of input terminals, a current transformer and a rectifierconnecting said input terminals to said system, a first chargingresistor having one end connected to one of said input terminals, asecond charging resistor and a transistor, said second resistor and theemitter-base circuit of said transistor being connected in parallel withsaid first charging resistor, energy storage means connected between thecollector of said transistor and the other input terminal, whereby saidenergy storage means is chargeable by a predetermined portion of thecurrent flowing at said input terminals.

12. An electronic timing device comprising a pair of input terminals, afirst current dividing resistor having one end connected to one of saidinput terminals, a second current divid ing resistor and a chargingtransistor, said second current dividing resistor and the emitter-basecircuit of said charging transistor being connected in parallel withsaid first current dividing resistor, a timing capacitor connectedbetween the collector of said coupling transistor and said other inputterminal and adapted to be charged by the current flowing therein, apower capacitor connected to the other end of said first currentdividing resistor, and voltage responsive means connected to said timingcapacitor for actuation when the charge on said timing capacitor reachesa predetermined value, said power capacitor means being connected tosaid voltage responsive means for supplying operating energy thereto.

13. A circuit interrupting device for protecting an electrical systemfrom overload currents, switch means for interrupting the current insaid system,timing capacitor means coupled to said system, firstimpedance means coupled to said timing capacitor means for controllingthe charging rate thereof as a function of the magnitude of the currentin said system, second impedance means in circuit with said timingcapacitor means for controlling the charging rate thereof independentlyof the magnitude of the current in said system, third impedance meanscoupled to said timing capacitor means for normally holding the same ina discharged condition, overload responsive means coupled to said systemand operable when the current therein exceeds a predetermined value toconduct current to said third impedance means so as to raise the voltagedrop thereacross and to prevent the further discharge of said capacitormeans therethrough so that said charging capacitor may begin charging,and uni-directional current means for preventing current flow from saidthird impedance means to said timing capacitor means, and output meanscoupled to said capacitor means and operable to open said switch meanswhen the charge thereon reaches a predetermined value.

14. A circuit interrupter for protecting an electrical system fromoverload currents, switch means in circuit with said system forinterrupting the current flow therein, timing capacitor means coupled tosaid system, first resistance means in series circuit relation with saidtiming capacitor means for controlling the charging rate thereof as afunction of the mag nitude of the current in said system, secondresistance means in parallel circuit relation with said timing capacitormeans for controlling the charging rate thereof independently of themagnitude of the current in said system, third resistance meansconnected in parallel circuit relation with said timing capacitor meansfor normally holding the same in a discharged condition, overloadresponsive means coupled to said system and responsive to apredetermined current therein for conducting current to said thirdresistance means to raise the voltage drop thereacross so that saidtiming capacitor is prevented from discharging therethrough, wherebysaid timing capacitor begins charging when the current in said systemreaches a predetermined value, uni-directional current means forpreventing current from flowing from said third resistance means to saidtiming capacitor means, and output means coupled to said timingcapacitor means and operable when the charge thereon reaches apredetermined value for opening said switch means.

15. In an electronic timing device having an input con nected to anelectric system, timing capacitor means, circuit means coupled to saidinput for charging said timing capacitor means by a current functionallyrelated to the current in said input, leakage means normally shuntingsaid timing capacitor means for preventing the charging thereof, anenergy source, abnormal condition responsive means coupled to saidinput, switching means coupled to said leakage means and to said energysource, said overload responsive means being operative upon theoccurrence of an abnormal circuit condition to actuate said switchingmeans to couple said leakage means to said energy source for modifyingthe potential of said leakage means to thereby prevent the discharge ofsaid timing capacitor means therethrough whereby said timing capacitormeans is allowed to charge up, output means coupled to said timingcapacitor means and operative to interrupt said system when the chargeon said timing capacitor means reaches a predetermined level, andunidirectional current means for preventing current flow from saidleakage means to said timing capacitor means.

16. in a circuit interrupter for protecting an electrical system, anelectronic timing device having an input coupled to said system forderiving an electrical signal functionally re-' lated to the currenttherein, an energy source, energy storage means, electronic circuitmeans having a control element connected to said energy source, anoutput element connected to said energy storage means and an inputelement connected to said input, said electronic circuit means beingcharacterized in that current will flow from said output element whenthe ratio of the output element potential to the control elementpotential is within a predetermined range of values, whereby the maximumenergy potential applied to said energy storage means cannot exceed apredetermined value, and energy responsive means coupled to said energystorage means and responsive when the energy thereon reaches apredetermined value.

17. A circuit interrupter for protecting an electrical system, anelectronic timing device having an input coupled to said system forderiving an electrical signal functionally related to the currenttherein, an energy source, a transistor, energy storage means, theemitter and collector of said transistor being connected to said inputfor receiving said signal, the emitter and base of said transistorconnecting said energy storage means to said energy source whereby themaximum energy potential applied to said energy storage means cannotexceed the potential energy of said source, and energy responsive meanscoupled to said energy storage means and responsive when the chargethereon reaches a predetermined value.

18. In an electronic timing device the combination of a pair of inputterminals, a first resistance having one end connected to one of saidinput terminals, a second resistance and a transistor, said secondresistance and the emitter base circuit of said transistor beingconnected in parallel with said first resistance, a voltage sourceconnected to the other end of said first resistance, energy storagemeans connected to the collector of said transistor for charging by thecurrent flowing in said second resistance, whereby the voltage appliedto said energy storage means cannot exceed the voltage of said energysource, and energy responsive means coupled to said energy storage meansand responsive when the energy stored therein reaches a predeterminedvalue.

19. In an electronic timing device having an input connected to anelectrical system, timing capacitor means coupled to said input, leakageresistor means normally shunting said timing capacitor means forpreventing the charging thereof by the current flowing to said input, anenergy source, circuit means coupled to said input and to said leakageresistor means and including abnormal condition responsive means andswitching means having a control element connected to said abnormalcondition responsive means and output means operative to connect saidresistor means to said energy source, said overload responsive meansbeing operative upon the occurrence of an abnormal circuit condition toprovide an actuating signal to said control element so that saidresistor means is connected to said energy source for modifying thepotential thereof and prevent discharge of said timing capacitortherethrough, whereby said timing capacitor means is allowed to chargeup, output means coupled to said timing capacitor means and operative tointerrupt said system when the charge on said capacitor means reaches apredetermined level, and unidirectional current means for preventingcurrent flow from said leakage resistor means to said timing capacitormeans.

20. In an electronic timing device having an input connected to anelectrical system, timing capacitor means coupled to said input, leakageresistor means normally shunting said timing capacitor means forpreventing the charging thereof by the current flowing to said input,abnormal condition responsive means coupled to said input, electroniccircuit means coupled to said leakage resistor means, said overloadresponsive means being operative upon the occurrence of an abnormalcircuit condition to cause said electronic circuit means to conductcurrent to said leakage resistor for modifying the potential thereof andprevent discharge of said timing capacitor means therethrough, wherebysaid capacitor means is allowed to charge up, output means coupled tosaid timing capacitor means and operative to interrupt said system whenthe charge on said capacitor means reaches a predetermined level, andunidirectional current means for preventing current flow from saidleakage resistor means to said timing capacitor means.

21. In an electronic timing device having an input connected to anelectrical system, timing capacitor means coupled to said input, leakageresistor means normally shunting said timing capacitor means forpreventing the charging thereof by the current flowing to said input,abnormal condition responsive means coupled to said input, transistormeans having a base connected to said abnormal condition responsivemeans and an emitter-collector circuit connected to said leakageresistor, said overload responsive means being operative upon theoccurrence of an abnormal circuit condition to cause said transistor toconduct current to said leakage resistor for modifying the voltage dropthereacross and prevent the discharge of said timing capacitor meanstherethrough, whereby said timing capacitor means is allowed to chargeup, output means coupled to said timing capacitor means and operative tointerrupt said system when the charge in said capacitor means reaches apredetermined level, and unidirectional current means for preventingcurrent flow from said leakage resistor means to said timing capacitormeans.

22. In a circuit interrupter for protecting an electrical system, anelectronic timing device having an input coupled to said system forderiving an electrical signal functionally related to the currenttherein, an energy source, energy storage means, electronic circuitmeans having a control element connected to said energy source, anoutput element connected to said energy storage means and an inputelement connected to said input, said electronic circuit means beingoperative to conduct input current to said output when the ratio of theoutput element potential to the control element potential is less than apredetermined value, whereby said energy source is chargeable by acurrent functionally related to said signal until the potential thereofreaches a predetermined value, leakage impedance means normally shuntingsaid energy storage means to prevent the charging thereof, abnormalcondition responsive means coupled to said input and to said impedancemeans and operative to couple said impedance means to said energy sourceupon the occurrence of an abnormal circuit condition so that potentialof said impedance means is modified to prevent the further discharge ofsaid energy storage means therethrough, unidirectional current means forpreventing the flow of current from said impedance means to said energystorage means, and energy responsive means coupled to said energystorage means and responsive when the energy thereon reaches apredetermined value.

23. A circuit interrupter for protecting an electrical system, anelectronic timing device having an input coupled to said system forderiving an electrical system functionally related to the currenttherein, an energy source, a timing capacitor, a transistor, the emitterand base of said transistor being connected to said input for receivingsaid signal, the collector and base of said transister connecting saidenergy storage means to said energy source whereby the maximum energypotential applied to said energy storage means cannot exceed thepotential of said energy source, leakage resistor means normallyshunting said timing capacitor for preventing the charging thereof,abnormal condition responsive means connected to said input, switchingmeans coupled to said abnormal condition responsive means and to saidleakage resistor means and to said energy source, said overloadresponsive means being operative upon the occurrence of an abnormalcircuit condition to provide an actuating signal to said switching meansso that said leakage resistor means is connected to said energy source,for modifying the potential thereof and prevent the discharge of saidtiming capacitor therethrough, whereby said timing capacitor is allowedto charge up, output means coupled to said timing capacitor means andoperative to interrupt said system when the charge on said capacitormeans reaches a predetermined level, and unidirectional current meansfor preventing current flow from said leakage resistor means to saidcapacitor means.

24. In a protective relay assembly, a pair of terminals, means forderiving from current supplied to the pair of terminals a first directvoltage having a magnitude dependent on the magnitude of current flowingthrough the pair of terminals over a substantial range of variation ofthe magnitude of said current, means for deriving from current suppliedto said pair of terminals a second direct voltage, having a magnitudewhich is substantially constant over said range of variation, acapacitor, circuit means connecting the capacitor for energization inaccordance with the first direct voltage, said circuit means includingsubstantial resistance whereby the circuit means and capacitor provide atime-delay circuit, controllable disabling means rendering saidcapacitor ineffective for receiving a charge through said circuit means,effectuating means responsive to a predetermined relation between thefirst and second direct voltages for controlling the disabling means tocondition the capacitor to receive charge from said circuit means andtranslating means responsive to the voltage across said capacitor.

25. For use in protecting current distribution networks staticovercurrent relay means responsive to overcurrent conditions foroperating circuit protective devices after a predetermined time periodand before the network is damaged comprising first means for generatinga DC voltage representative of the current being monitored in saidnetwork; second means coupled to said first means for generating apredetermined voltage level after a predetermined time delay; thirdmeans coupled to said first means and normally inhibiting the operationof said second means until the output voltage level of said first meansachieves a predetermined magnitude; constant voltage reference meanscoupled to the output of said first means for establishing a secondpredetermined threshold level; fourth voltage-sensitive switch meanscoupled to said second means and said constant voltage reference meansfor energizing a circuit protective device when the output voltage ofsaid second means achieves said second predetermined threshold level.

26. The device of claim 25 wherein said first means is comprised ofcurrent transformer means; and full wave rectification means connectedacross the output of said current transformer means for generating saidDC voltage.

27. The device of claim 25 wherein said constant voltage reference meansis comprised of a series connected zener diode and resistor coupledbetween the output of said first means and ground potential; the commonterminal between said zener diode and resistor being coupled to saidfourth means.

28. The device of claim 27 wherein said fourth means is comprised oftransistor means having first, second and third electrodes,respectively, coupled to said constant reference voltage means commonterminal, the output of said second means, and said first means.

* l l t Po-wo UNITED STATES'PATENT OFFICE 569 CERTIFICATE OF CORRECTIONPatent No. 3 3, a 220 I Dated May 9 1972 lnventofls) 7 Richard E. RiebsIt is certified that error appears in the above-identified patent andthat said Letters Patent are hereby corrected as shown below:

r- I Column 18, line 57, cancel "overload" and substitute therefor-abnormal condition Column 19, line 46, cancel "overload" and substitutetherefor abnormal condition--- line 64, cancel "overload" and substitutetherefor -abnorma1 condition Column 20, line 9, cancel "overload" andsubstitute therefor -abn0rmal condition--;

line 48, cancel "system" (second occurrence) and substitutethereforsignal-.-;

line' 60, cancel "overload" and substitute therefor --abnormal conditionSigned and sealed this 26th day of December 1972.

(SEAL) Attest:

iE Q W- E Q B RJR. RoBERT GOTTS CHALKR u seeing flcer Commissioner ofPatents FORM PO-1050 (10-69) USCOMM-DC 60376-1 69 r us. GOVERNMENTPRINTING OFFICE: 19" o-ass-au,

37 UNITED STATES PATENT OFFICE QE TEHQATE F CGR Patent No. 3 a 662 220Dated May 9, 1972 Inventor(s) Richard E. RiebS It is certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

F- Column 18, line 57, cancel "overload" and substitute thereforabnorma1 condition;

Column 19, line 46, cancel "overload" and substitute therefor -abnorma1condition--;

line 64, cancel "overload" and substitute therefor abnormal conditionColumn 20, line 9, cancel "overload" and substitute therefor abnormalc0ndition;

line 48, cancel "system" (second occurrence) and substitute thereforsignal;

Signed and sealed this 26th day of December 1972.

(SEAL) Attest:

EDWARD I"I.FLETCHER,JR.

testing Officer ROBERT GOT'ISCHALK Commissioner of Patents ORM PO-105O(10-69) USCOMM-DC 60376-P69 r: us. GOVERNMENT PRINTING OFFICE: 19690-366-334.

1. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor coupled to saidinput and chargable by the current flowing therein, leakage resistormeans normally shunting said timing capacitor for preventing thecharging thereof by the current flowing to said input, normally inactiveelectronic circuit means coupled to said input and to said timingcapacitor and responsive to an abnormal circuit condition in said systemfor conducting current to said resistor means to modify the voltage dropthereacross and prevent the discharge of said capacitor through saidleakage resistor means upon the occurrence of said abnormal circuitcondition so that said timing capacitor may begin charging.
 2. In anelectronic timing device having an input adapted to be connected to anelectrical system, energy storage means coupled to said input, leakageresistor means normally shunting said energy storage means forpreventing the charging thereoF by the current flowing to said input,overload sensing means coupled to said input and normally inactiveelectronic means coupled to said leakage resistor means, said overloadsensing means being responsive to the current in said system to actuatesaid electronic circuit means for raising the voltage drop across saidleakage resistor means to thereby prevent the discharge of said energystorage means therethrough when the current in said system reaches apredetermined value, whereby said energy storage means is allowed tocharge up.
 3. In an electronic timing device having an input adapted tobe connected to an electrical system, timing capacitor means coupled tosaid input, leakage resistor means normally shunting said timingcapacitor for preventing the charging thereof by the current flowing tosaid input, circuit means including overload sensing means coupled tosaid input and normally inactive electronic means coupled to saidleakage resistor means, said overload sensing means being responsive tothe current in said system to actuate said electronic means to conductcurrent to said leakage resistor to raise the voltage drop thereacrossto thereby prevent the discharge of said timing capacitor meanstherethrough when the current in said system reaches a predeterminedvalue, whereby said energy storage means is allowed to charge up, andmeans for preventing current from flowing from said leakage resistormeans to said timing capacitor means.
 4. An electronic timing devicecomprising an input adapted to be connected to an electrical system, atiming capacitor connected to said input and chargeable by the currentflowing therein, a leakage resistor shunting said timing capacitor,voltage comparison means having sensing means and reference voltagemeans, said voltage comparison means also having output means connectedto said leakage resistor means, said voltage comparison means beingactuable when the voltage at said sensing means exceeds said referencevoltage to conduct current to said leakage resistor means, circuit meansconnecting said sensing means to said input for placing a voltage onsaid sensing means that is proportional to the current at said inputwhereby output current will flow to said leakage resistor when thecurrent at said input exceeds a predetermined value to thereby raise itsvoltage to a value higher than the voltage across said timing capacitorso that the further discharge thereof is prevented, unidirectionalcircuit means for preventing current flow from said leakage resistormeans to said timing capacitor, and output means coupled to said timingcapacitor and operable when the charge thereon exceeds a predeterminedvalue.
 5. An electronic timing device comprising an input adapted to beconnected to an electrical system, a timing capacitor connected to saidinput and chargeable by the current flowing therein, a leakage resistorshunting said timing capacitor, a signal responsive transistor,reference voltage means, circuit means connecting the base of saidsignal responsive transistor to said input for placing a potential onsaid base that is proportional to the current at said input, the emitterof said transistor being connected to said reference voltage meanswhereby collector current will flow in said transistor when the currentat said input exceeds a predetermined value, normally non-conductingcurrent responsive means connected to said leakage resistor and to thecollector of said transistor so that when collector current flowstherein as a result of said predetermined current at said input saidcurrent responsive circuit means will conduct current to said leakageresistor to thereby raise its voltage to a value higher than the voltageacross said timing capacitor so that the further discharge thereof isprevented, and diode means for preventing current from flowing from saidleakage resistor to said timing capacitor.
 6. An electronic timingdevice comprising an input adapted to be connected to an electricalsystem, a timing caPacitor connected to said input and chargeable by thecurrent flowing therein, a leakage resistor shunting said timingcapacitor, triode means having a source element, a load element and acontrol element, reference voltage means, circuit means connecting thecontrol element of said triode means to said input for placing apotential on said control element that is proportional to the current atsaid input, the source element of said triode means being connected tosaid reference voltage means whereby load current will flow in said loadelement when the current at said input exceeds a predetermined value,normally non-conducting current responsive means connected to saidleakage resistor and to said load element so that when load currentflows in said triode means as a result of said predetermined current atsaid input said current responsive means will conduct current to saidleakage resistor to thereby raise its voltage to a value higher than thevoltage across said timing capacitor so that the further dischargethereof is prevented, and output means coupled to said timing capacitorand operable when the charge thereon exceeds a predetermined value. 7.An electronic timing device comprising an input adapted to be connectedto an electrical system, a timing capacitor coupled to said input andchargeable by the current flowing therein, leakage resistor meansconnected in parallel with said timing capacitor for normally shuntingsaid charging current therearound, voltage biasing means connected tosaid leakage resistor means in a sense opposite to the sense of saidshunted current so that the effect of the voltage drop across saidleakage resistor on the potential of the junction between said leakageresistor and said timing capacitor is partially cancelled, rectifiermeans shunting said timing capacitor and operable to shunt around saidtiming capacitor any reverse current from said leakage resistor as aresult of said biasing means whereby the voltage drop in said leakageresistor as a result of said leakage current does not produce adifference in potential across said timing capacitor, circuit meanscoupled to said input and responsive to the current in said system forpreventing the discharge of said capacitor through said leakage resistormeans when the current in said system reaches a predetermined value. 8.An electronic timing device comprising an input adapted to be connectedto an electrical system, a timing capacitor connected to said input andchargeable by the current flowing therein, a leakage resistor connectedin parallel with said timing capacitor for shunting said chargingcurrent therearound; means coupled to said timing capacitor and to saidleakage resistor means for cancelling the effect of the shunted currentproduced voltage drop across said leakage resistor on said timingcapacitor means whereby the voltage drop in said leakage resistor doesnot produce a potential difference across said timing capacitor, voltagecomparison means having sensing means and reference voltage means, saidvoltage comparison means also including output means connected to saidleakage resistor means said voltage comparison means being actuable whenthe voltage at said sensing means exceeds said reference voltage toconduct current to said leakage resistor means, circuit means connectingsaid sensing means to said input for placing a voltage on said sensingmeans that is proportional to the current at said input whereby outputcurrent will flow to said leakage resistor to thereby raise its voltageto a value higher than the voltage across said timing capacitor so thatthe further discharge thereof is prevented.
 9. In an electronic timingdevice the combination of an input adapted to be connected to anelectrical system, timing capacitor means connected to said input andchargeable by the current flowing therein, an impedance in a parallelcircuit with respect to said timing capacitor means for shunting aportion of said current around said timing capacitor said paralLelcircuit including means for holding said shunted current to apredetermined value, leakage means connected to said capacitor andnormally preventing the charging thereof, said energy leakage meansincluding circuit means connected to said input and responsive to apredetermined current in said system for preventing the leakage of saidcurrent means through said leakage means so that said timing capacitormeans beings charging upon the occurrence of said predetermined current.10. In an electronic timing device the combination of a pair of inputterminals, a first charging resistor having one end connected to one ofsaid input terminals, a second charging resistor and a transistor, saidsecond resistor and the emitter-base circuit of said transistor beingconnected in parallel with said first charging resistor, a first energystorage means between the other end of said first resistor and the otherinput terminal, a second energy storage means connected between thecollector of said transistor and said other input terminal, whereby eachof said energy storage means is chargeable by the current flowing in itsassociated resistor, energy responsive means coupled to said firstenergy storage means and responsive to the energy stored therein foractuation when the energy on said first energy storage means reaches apredetermined value, said second energy storage means being connected tosaid energy responsive means for supplying operating energy thereto. 11.In a device for protecting an electrical system, the combination of apair of input terminals, a current transformer and a rectifierconnecting said input terminals to said system, a first chargingresistor having one end connected to one of said input terminals, asecond charging resistor and a transistor, said second resistor and theemitter-base circuit of said transistor being connected in parallel withsaid first charging resistor, energy storage means connected between thecollector of said transistor and the other input terminal, whereby saidenergy storage means is chargeable by a predetermined portion of thecurrent flowing at said input terminals.
 12. An electronic timing devicecomprising a pair of input terminals, a first current dividing resistorhaving one end connected to one of said input terminals, a secondcurrent dividing resistor and a charging transistor, said second currentdividing resistor and the emitter-base circuit of said chargingtransistor being connected in parallel with said first current dividingresistor, a timing capacitor connected between the collector of saidcoupling transistor and said other input terminal and adapted to becharged by the current flowing therein, a power capacitor connected tothe other end of said first current dividing resistor, and voltageresponsive means connected to said timing capacitor for actuation whenthe charge on said timing capacitor reaches a predetermined value, saidpower capacitor means being connected to said voltage responsive meansfor supplying operating energy thereto.
 13. A circuit interruptingdevice for protecting an electrical system from overload currents,switch means for interrupting the current in said system, timingcapacitor means coupled to said system, first impedance means coupled tosaid timing capacitor means for controlling the charging rate thereof asa function of the magnitude of the current in said system, secondimpedance means in circuit with said timing capacitor means forcontrolling the charging rate thereof independently of the magnitude ofthe current in said system, third impedance means coupled to said timingcapacitor means for normally holding the same in a discharged condition,overload responsive means coupled to said system and operable when thecurrent therein exceeds a predetermined value to conduct current to saidthird impedance means so as to raise the voltage drop thereacross and toprevent the further discharge of said capacitor means therethrough sothat said charging capacitor may beGin charging, and uni-directionalcurrent means for preventing current flow from said third impedancemeans to said timing capacitor means, and output means coupled to saidcapacitor means and operable to open said switch means when the chargethereon reaches a predetermined value.
 14. A circuit interrupter forprotecting an electrical system from overload currents, switch means incircuit with said system for interrupting the current flow therein,timing capacitor means coupled to said system, first resistance means inseries circuit relation with said timing capacitor means for controllingthe charging rate thereof as a function of the magnitude of the currentin said system, second resistance means in parallel circuit relationwith said timing capacitor means for controlling the charging ratethereof independently of the magnitude of the current in said system,third resistance means connected in parallel circuit relation with saidtiming capacitor means for normally holding the same in a dischargedcondition, overload responsive means coupled to said system andresponsive to a predetermined current therein for conducting current tosaid third resistance means to raise the voltage drop thereacross sothat said timing capacitor is prevented from discharging therethrough,whereby said timing capacitor begins charging when the current in saidsystem reaches a predetermined value, uni-directional current means forpreventing current from flowing from said third resistance means to saidtiming capacitor means, and output means coupled to said timingcapacitor means and operable when the charge thereon reaches apredetermined value for opening said switch means.
 15. In an electronictiming device having an input connected to an electric system, timingcapacitor means, circuit means coupled to said input for charging saidtiming capacitor means by a current functionally related to the currentin said input, leakage means normally shunting said timing capacitormeans for preventing the charging thereof, an energy source, abnormalcondition responsive means coupled to said input, switching meanscoupled to said leakage means and to said energy source, said overloadresponsive means being operative upon the occurrence of an abnormalcircuit condition to actuate said switching means to couple said leakagemeans to said energy source for modifying the potential of said leakagemeans to thereby prevent the discharge of said timing capacitor meanstherethrough whereby said timing capacitor means is allowed to chargeup, output means coupled to said timing capacitor means and operative tointerrupt said system when the charge on said timing capacitor meansreaches a predetermined level, and unidirectional current means forpreventing current flow from said leakage means to said timing capacitormeans.
 16. In a circuit interrupter for protecting an electrical system,an electronic timing device having an input coupled to said system forderiving an electrical signal functionally related to the currenttherein, an energy source, energy storage means, electronic circuitmeans having a control element connected to said energy source, anoutput element connected to said energy storage means and an inputelement connected to said input, said electronic circuit means beingcharacterized in that current will flow from said output element whenthe ratio of the output element potential to the control elementpotential is within a predetermined range of values, whereby the maximumenergy potential applied to said energy storage means cannot exceed apredetermined value, and energy responsive means coupled to said energystorage means and responsive when the energy thereon reaches apredetermined value.
 17. A circuit interrupter for protecting anelectrical system, an electronic timing device having an input coupledto said system for deriving an electrical signal functionally related tothe current therein, an energy source, a transistor, energy storagemeans, the emitter and collector of said transistor being connected tosaid input for receiving said signal, the emitter and base of saidtransistor connecting said energy storage means to said energy sourcewhereby the maximum energy potential applied to said energy storagemeans cannot exceed the potential energy of said source, and energyresponsive means coupled to said energy storage means and responsivewhen the charge thereon reaches a predetermined value.
 18. In anelectronic timing device the combination of a pair of input terminals, afirst resistance having one end connected to one of said inputterminals, a second resistance and a transistor, said second resistanceand the emitter base circuit of said transistor being connected inparallel with said first resistance, a voltage source connected to theother end of said first resistance, energy storage means connected tothe collector of said transistor for charging by the current flowing insaid second resistance, whereby the voltage applied to said energystorage means cannot exceed the voltage of said energy source, andenergy responsive means coupled to said energy storage means andresponsive when the energy stored therein reaches a predetermined value.19. In an electronic timing device having an input connected to anelectrical system, timing capacitor means coupled to said input, leakageresistor means normally shunting said timing capacitor means forpreventing the charging thereof by the current flowing to said input, anenergy source, circuit means coupled to said input and to said leakageresistor means and including abnormal condition responsive means andswitching means having a control element connected to said abnormalcondition responsive means and output means operative to connect saidresistor means to said energy source, said overload responsive meansbeing operative upon the occurrence of an abnormal circuit condition toprovide an actuating signal to said control element so that saidresistor means is connected to said energy source for modifying thepotential thereof and prevent discharge of said timing capacitortherethrough, whereby said timing capacitor means is allowed to chargeup, output means coupled to said timing capacitor means and operative tointerrupt said system when the charge on said capacitor means reaches apredetermined level, and unidirectional current means for preventingcurrent flow from said leakage resistor means to said timing capacitormeans.
 20. In an electronic timing device having an input connected toan electrical system, timing capacitor means coupled to said input,leakage resistor means normally shunting said timing capacitor means forpreventing the charging thereof by the current flowing to said input,abnormal condition responsive means coupled to said input, electroniccircuit means coupled to said leakage resistor means, said overloadresponsive means being operative upon the occurrence of an abnormalcircuit condition to cause said electronic circuit means to conductcurrent to said leakage resistor for modifying the potential thereof andprevent discharge of said timing capacitor means therethrough, wherebysaid capacitor means is allowed to charge up, output means coupled tosaid timing capacitor means and operative to interrupt said system whenthe charge on said capacitor means reaches a predetermined level, andunidirectional current means for preventing current flow from saidleakage resistor means to said timing capacitor means.
 21. In anelectronic timing device having an input connected to an electricalsystem, timing capacitor means coupled to said input, leakage resistormeans normally shunting said timing capacitor means for preventing thecharging thereof by the current flowing to said input, abnormalcondition responsive means coupled to said input, transistor meanshaving a base connected to said abnormal condition responsive means andan emitter-collector circuit connected to said leakage resistor, saidoverload responsive means being operative upon the ocCurrence of anabnormal circuit condition to cause said transistor to conduct currentto said leakage resistor for modifying the voltage drop thereacross andprevent the discharge of said timing capacitor means therethrough,whereby said timing capacitor means is allowed to charge up, outputmeans coupled to said timing capacitor means and operative to interruptsaid system when the charge in said capacitor means reaches apredetermined level, and unidirectional current means for preventingcurrent flow from said leakage resistor means to said timing capacitormeans.
 22. In a circuit interrupter for protecting an electrical system,an electronic timing device having an input coupled to said system forderiving an electrical signal functionally related to the currenttherein, an energy source, energy storage means, electronic circuitmeans having a control element connected to said energy source, anoutput element connected to said energy storage means and an inputelement connected to said input, said electronic circuit means beingoperative to conduct input current to said output when the ratio of theoutput element potential to the control element potential is less than apredetermined value, whereby said energy source is chargeable by acurrent functionally related to said signal until the potential thereofreaches a predetermined value, leakage impedance means normally shuntingsaid energy storage means to prevent the charging thereof, abnormalcondition responsive means coupled to said input and to said impedancemeans and operative to couple said impedance means to said energy sourceupon the occurrence of an abnormal circuit condition so that potentialof said impedance means is modified to prevent the further discharge ofsaid energy storage means therethrough, unidirectional current means forpreventing the flow of current from said impedance means to said energystorage means, and energy responsive means coupled to said energystorage means and responsive when the energy thereon reaches apredetermined value.
 23. A circuit interrupter for protecting anelectrical system, an electronic timing device having an input coupledto said system for deriving an electrical system functionally related tothe current therein, an energy source, a timing capacitor, a transistor,the emitter and base of said transistor being connected to said inputfor receiving said signal, the collector and base of said transisterconnecting said energy storage means to said energy source whereby themaximum energy potential applied to said energy storage means cannotexceed the potential of said energy source, leakage resistor meansnormally shunting said timing capacitor for preventing the chargingthereof, abnormal condition responsive means connected to said input,switching means coupled to said abnormal condition responsive means andto said leakage resistor means and to said energy source, said overloadresponsive means being operative upon the occurrence of an abnormalcircuit condition to provide an actuating signal to said switching meansso that said leakage resistor means is connected to said energy source,for modifying the potential thereof and prevent the discharge of saidtiming capacitor therethrough, whereby said timing capacitor is allowedto charge up, output means coupled to said timing capacitor means andoperative to interrupt said system when the charge on said capacitormeans reaches a predetermined level, and unidirectional current meansfor preventing current flow from said leakage resistor means to saidcapacitor means.
 24. In a protective relay assembly, a pair ofterminals, means for deriving from current supplied to the pair ofterminals a first direct voltage having a magnitude dependent on themagnitude of current flowing through the pair of terminals over asubstantial range of variation of the magnitude of said current, meansfor deriving from current supplied to said pair of terminals a seconddirect voltage, having a magnitude which is substantially constant oversaid range of variation, a capacitor, circuit means connecting thecapacitor for energization in accordance with the first direct voltage,said circuit means including substantial resistance whereby the circuitmeans and capacitor provide a time-delay circuit, controllable disablingmeans rendering said capacitor ineffective for receiving a chargethrough said circuit means, effectuating means responsive to apredetermined relation between the first and second direct voltages forcontrolling the disabling means to condition the capacitor to receivecharge from said circuit means and translating means responsive to thevoltage across said capacitor.
 25. For use in protecting currentdistribution networks static overcurrent relay means responsive toovercurrent conditions for operating circuit protective devices after apredetermined time period and before the network is damaged comprisingfirst means for generating a DC voltage representative of the currentbeing monitored in said network; second means coupled to said firstmeans for generating a predetermined voltage level after a predeterminedtime delay; third means coupled to said first means and normallyinhibiting the operation of said second means until the output voltagelevel of said first means achieves a predetermined magnitude; constantvoltage reference means coupled to the output of said first means forestablishing a second predetermined threshold level; fourthvoltage-sensitive switch means coupled to said second means and saidconstant voltage reference means for energizing a circuit protectivedevice when the output voltage of said second means achieves said secondpredetermined threshold level.
 26. The device of claim 25 wherein saidfirst means is comprised of current transformer means; and full waverectification means connected across the output of said currenttransformer means for generating said DC voltage.
 27. The device ofclaim 25 wherein said constant voltage reference means is comprised of aseries connected zener diode and resistor coupled between the output ofsaid first means and ground potential; the common terminal between saidzener diode and resistor being coupled to said fourth means.
 28. Thedevice of claim 27 wherein said fourth means is comprised of transistormeans having first, second and third electrodes, respectively, coupledto said constant reference voltage means common terminal, the output ofsaid second means, and said first means.